Monolithic ICs generally comprise a number passive devices, such as resistors, and/or active devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), or the like, fabricated over a substrate. Current system on a chip (SoC) technologies are focused on aggressively scaling the FET gate length (Lg) to provide performance and area scaling in accordance with Moore's Law.
One adverse effect of lateral scaling is that the support for low leakage and high voltage devices, both of which are important in SoC applications, becomes more difficult due to the architecture of high voltage transistors diverging from that of the minimum design-rule (nominal) logic transistor. Lateral scaling also reduces gate-contact spacing, which increases the peak electric field, further reducing a transistor's high voltage operating window.
A device architecture which enables some transistors to have a larger gate-drain spacing and/or to withstand higher breakdown voltages for a given gate-drain separation is advantageous for complex monolithic SOC IC designs.